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3-1 semiconductor january 1999 ca3060 110khz, operational transconductance ampli?er array caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1999 file number 537.4 features ? low power consumption as low as 100mw per ampli?er ? independent biasing for each ampli?er ? high forward transconductance ? programmable range of input characteristics ? low input bias and input offset current ? high input and output impedance ? no effect on device under output short-circuit conditions ? zener diode bias regulator applications ? for low power conventional operational ampli?er applications ? active filters ? comparators ? gyrators ? mixers ? modulators ? multiplexers ? multipliers ? strobing and gating functions ? sample and hold functions description the ca3060 monolithic integrated circuit consists of an array of three independent operational transconductance ampli?ers (see note). this type of ampli?er has the generic characteris- tics of an operational voltage ampli?er with the exception that the forward gain characteristic is best described by transcon- ductance rather than voltage gain (open-loop voltage gain is the product of the transconductance and the load resistance, g m r l ). when operated into a suitable load resistor and with provisions for feedback, these ampli?ers are well suited for a wide variety of operational-ampli?er and related applications. in addition, the extremely high output impedance makes these types particularly well suited for service in active ?lters. the three ampli?ers in the ca3060 are identical push-pull class a types which can be independently biased to achieve a wide range of characteristics for speci?c application. the elec- trical characteristics of each ampli?er are a function of the ampli?er bias current (i abc ). this feature offers the system designer maximum ?exibility with regard to output current capa- bility, power consumption, slew rate, input resistance, input bias current, and input offset current. the linear variation of the parameters with respect to bias and the ability to maintain a constant dc level between input and output of each ampli?er also makes the ca3060 suitable for a variety of nonlinear appli- cations such as mixers, multipliers, and modulators. in addition, the ca3060 incorporates a unique zener diode regulator system that permits current regulation below sup- ply voltages normally associated with such systems. note: generic applications of the ota are described in an-6668. for improved input operating ranges, refer to ca3080 and ca3280 data sheets (file nos. 475 and 1174) and application notes an6668 and an6818. pinout ca3060 (pdip) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 + + + amp 1 bias reg. regulator out regulator in v+ inv. input no. 3 non-inv. input no. 3 bias no. 3 output no. 3 v- output no. 1 bias no. 1 non-inv. input no. 1 inv. input no. 1 inv. input no. 2 non-inv. input no. 2 bias no. 2 output no. 2 amp 3 amp 2 part number information part number temp. range ( o c) package pkg. no. CA3060E -40 to 85 16 ld pdip e16.3 [ /title (ca30 60) /sub- ject (110k hz, opera- tional transc onduc- tance ampli- ?er array) /autho r () /key- words (har- ris semi- con- ductor, triple, transco nduc- tance ampli- ?er, low power op amp, obsolete product no recommended repla cement call central applications 1-800-442-7747 or email: centapp@harris.com
3-2 absolute maximum ratings operating conditions supply voltage (between v+ and v- terminals) . . . . . . . 36v ( 18v) input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to v- differential input voltage (each ampli?er) . . . . . . . . . . . . . . . . . . 5v input current (each ampli?er) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma ampli?er bias current (each ampli?er) . . . . . . . . . . . . . . . . . . . 2ma bias regulator input current . . . . . . . . . . . . . . . . . . . . . . . . . . -5ma output short circuit duration (note 1) . . . . . . . . . . . . . . . . inde?nite temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal information thermal resistance (typical, note 2) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 maximum junction temperature (plastic package) . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. notes: 1. short circuit may be applied to ground or to either supply. 2. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations t a = 25 o c, v supply = 15v parameter symbol amplifier bias current units i abc = 1 m ai abc = 10 m ai abc = 100 m a min typ max min typ max min typ max input offset voltage (see figure 1) v io -1- -1- -15mv input offset current (see figure 2) i io - 3 - - 30 - - 250 1000 na input bias current (see figures 3, 4) i ib - 33 - - 300 - - 2500 5000 na peak output current (see figures 5, 6) i om - 2.3 - - 26 - 150 240 - m a peak output voltage (see figure 7) positive v om + - 13.6 - - 13.6 - 12 13.6 - v negative v om - - 14.7 - - 14.7 - 12 14.7 - v amplifier supply current (each amplifier) (see figures 8, 9) i a - 8.5 - - 85 - - 850 1200 m a power consumption (each amplifier) p - 0.26 - - 2.6 - - 26 36 mw input offset voltage sensitivity (note 3) positive d v io / d v+ - 1.5 - - 2 - - 2 150 m v/v negative d v io / d v--20- -20- -30150 m v/v amplifier bias voltage (note 4, see figure 10) v abc - 0.54 - - 0.60 - - 0.66 - v dynamic characteristics at 1khz, unless otherwise specified forward transconductance (large signal) (see figures 11, 12) g 21 - 1.55 - - 18 - 30 102 - ms common mode rejection ratio cmrr - 110 - - 110 - 70 90 - db common mode input voltage range v icr +12 to -12 +13 to -14 - +12 to -12 +13 to -14 - +12 to -12 +13 to -14 -v slew rate (test circuit) (see figure 17) sr - 0.1 - - 1 - - 8 - v/ m s open loop (g 21 ) bandwidth (see figure 13) bw ol - 20 - - 45 - - 110 - khz ca3060
3-3 input impedance components resistance (see figure 14) r i - 1600 - - 170 - 10 20 - k w capacitance at 1mhz c i - 2.7 - - 2.7 - - 2.7 - pf output impedance components resistance (see figure 15) r o - 200 - - 20 - - 2 - m w capacitance at 1mhz c o - 4.5 - - 4.5 - - 4.5 - pf zener bias regulator characteristics i 2 = 0.1ma voltage (see figure 16) v z temperature coefficient = 3mv/ o c 6.2 6.7 7.9 v impedance z z - 200 300 w notes: 3. conditions for input offset voltage sensitivity: a. bias current derived from the regulator with an appropriate resistor connected from terminal 1 to the bias terminal on the am pli?er under test v+ is reduced to +13v for v+ sensitivity and v- is reduced to -13v for v- sensitivity. b. v+ sensitivity in , v- sensitivity in . 4. temperature coef?cient; -2.2mv/ o c (at v abc = 0.54, i abc = 1 m a); -2.1mv/ o c (at v abc = 0.060v, i abc = 10 m a); -1.9mv/ o c (at v abc = 0.66v, i abc = 100 m a) electrical speci?cations t a = 25 o c, v supply = 15v (continued) parameter symbol amplifier bias current units i abc = 1 m ai abc = 10 m ai abc = 100 m a min typ max min typ max min typ max m vv v offset v offset for +13v and -15v supplies C 1v ----------------------------------------------------------------------------------------------------------------------------- - = m vv v offset v offset for -13v and +15v supplies C 1v ----------------------------------------------------------------------------------------------------------------------------- - = schematic diagram bias regulator and one operational transconductance amplifier notes: 5. inverting input of amplifiers 1, 2 and 3 is on terminals 13, 12 and 4, respectively. 6. non-inverting input of amplifiers 1, 2 and 3 is terminals 14, 11 and 5, respectively. 7. amplifier bias current of amplifiers 1, 2 and 3 is on terminals 15, 10 and 6, respectively. 8. output of amplifiers 1, 2 and 3 is on terminals 16, 9 and 7, respectively. 2 1 d 4 d 5 q 10 inverting input q 1 q 2 d 1 - + i abc (note 5) non-inverting input (note 6) zener bias regulator amplifier bias input (note 7) q 3 q 6 q 7 d 2 q 5 3 8 d 3 q 8 output (note 8) v+ v- q 4 ca3060
3-4 typical performance curves figure 1. input offset voltage vs amplifier bias current figure 2. input offset current vs amplifier bias current figure 3. input bias current vs amplifier bias current figure 4. input bias current vs temperature figure 5. peak output current vs amplifier bias current figure 6. peak output current vs temperature 1 10 100 1000 2.0 1.5 1.0 0.5 0.0 amplifier bias current ( m a) input offset voltage (mv) 125 o c 25 o c -55 o c supply voltage: v s = 15 v s = 6 amplifier bias current ( m a) 1 10 100 1000 1000 100 10 1 input offset current (na) supply voltage: v s = 15 v s = 6 t a = 25 o c maximum typical 1 10 100 1000 amplifier bias current ( m a) 10 1 0.1 0.01 typical maximum input bias current ( m a) t a = 25 o c supply voltage: v s = 15 v s = 6 supply voltage: v s = 6 v s = 15 i abc = 100 m a i abc = 10 m a i abc = 1 m a -75 -50 -25 0 25 50 75 100 125 temperature ( o c) 10 1.0 0.1 0.01 input bias current ( m a) peak output current ( m a) typical minimum amplifier bias current ( m a) 1 10 100 1000 1000 100 10 1 t a = 25 o c supply voltage: v s = 15 v s = 6 1000 100 10 1 peak output current ( m a) -75 -50 -25 0 25 50 75 100 125 temperature ( o c) i abc = 100 m a i abc = 30 m a i abc = 10 m a i abc = 3 m a i abc = 1 m a supply voltage: v s = 6 v s = 15 ca3060
3-5 figure 7. peak output voltage vs amplifier bias current figure 8. amplifier supply current (each amplifier) vs amplifier bias current figure 9. amplifier supply current (each amplifier) vs temperature figure 10. amplifier bias voltage vs amplifier bias current figure 11. forward transconductance vs amplifier bias current figure 12. forward transconductance vs temperature typical performance curves (continued) 1 10 100 1000 14 13 12 6 5 4 3 -3 -4 -5 -6 -12 -13 -14 -15 amplifier bias current ( m a) peak output voltage (v) v om + (typ) 15v supply v om + (min) 15v supply v om + (typ) 6v supply v om + (min) 6v supply v om - (min) 6v supply v om - (typ) 6v supply v om - (min) 15v supply v om - (typ) 15v supply 1 10 100 1000 10,000 1000 100 10 amplifier bias current ( m a) amplifier supply current ( m a) maximum typical t a = 25 o c supply voltage: v s = 15 v s = 6 i abc = 100 m a i abc = 30 m a i abc = 10 m a i abc = 3 m a i abc = 1 m a 1000 100 10 1 -75 -50 -25 0 25 50 75 100 125 temperature ( o c) amplifier supply current ( m a) supply voltage: v+ = 6v, v- = -6v v+ = 15v, v- = -15v 800 750 700 650 600 550 500 amplifier bias voltage (mv) amplifier bias current ( m a) 1 10 100 1000 supply voltage: vv s = 6 v s = 15 t a = 25 o c, f = 1khz supply voltage: v s = 6 v s = 15 typical minimum 1000 100 10 1 1 10 100 1000 forward transconductance (ms) amplifier bias current ( m a) 1000 100 10 1 -50 -25 0 25 50 75 100 125 temperature ( o c) forward transconductance (s) i abc = 100 m a i abc = 30 m a i abc = 10 m a i abc = 1 m a t a = 25 o c, f = 1khz supply voltage: v s = 15 v s = 6 ca3060
3-6 figure 13. forward transconductance vs frequency figure 14. input resistance vs amplifier bias current figure 15. output resistance vs amplifier bias current figure 16. bias regulator voltage vs bias regulator current test circuit figure 17. slew rate test circuit for amplifier 1 of ca3060 typical performance curves (continued) forward transconductance (ms) phase angle (degrees) 100 10 1.0 0.1 0.01 0.001 0.01 0.1 1.0 10 100 frequency (mhz) 0 -50 -100 -150 -200 -250 -300 -350 i abc = 100 m a i abc = 10 m a i abc = 1 m a i abc = 10 m a i abc = 1 m a phase angle forward trans. t a = 25 o c supply voltage: v s = 15 v s = 6 t a = 25 o c, f = 1khz supply voltage: v s = 15 v s = 6 typical minimum 1 10 100 1000 amplifier bias current ( m a) 10,000 1000 100 10 input resistance (k w ) typical 1 10 100 1000 amplifier bias current ( m a) 1000 100 10 1 output resistance (m w ) t a = 25 o c, f = 1khz supply voltage: v s = 15 v s = 6 7.0 6.75 6.5 6.25 0 200 400 600 800 1000 1200 1400 typical t a = 25 o c supply voltage: v s = 15 v s = 6 bias regulator voltage (v) bias regulator current ( m a) v z is measured between terminal 1 and 8 v abc is measured between terminals 15 and 8 supply voltage: for both 6v and 15v typical slew rate test circuit parameters i abc slew rate i 2 r abc r s r f r b r c c c m av/ m s m a w wwwwm f 100 8 200 62k 100k 100k 51k 100 0.02 10 1 200 620k 1m 1m 510k 1k 0.005 1 0.1 2 6.2m 10m 10m 5.1m 0 r z v+ () v- () 0.7 C C [] i 2 ----------------------------------------------- - r abc , v z v abc C i abc ---------------------------- - == 2 8 1 15 amplifier 1 13 14 16 r abc i abc 10 m w out- put external load 13 pf 3 v- v+ r f c c r c r b r s r z i 2 - + in- put ca3060
3-7 application information the ca3060 consists of three operational ampli?ers similar in form and application to conventional operational ampli?ers but suf?ciently different from the standard operational ampli?er (op amp) to justify some explanation of their characteristics. the ampli?ers incorporated in the ca3060 are best described by the term operational transconduc- tance ampli?er (ota). the characteristics of an ideal ota are similar to those of an ideal op amp except that the ota has an extremely high output impedance. because of this inherent characteristics the output signal is best de?ned in terms of current which is proportional to the difference between the voltages of the two input terminals. thus, the transfer characteristics is best described in terms of transconductance rather than voltage gain. other than the difference given above, the characteristics tabulated are similar to those of any typical op amp. the ota circuitry incorporated in the ca3060 (figure 18) provides the equipment designer with a wider variety of circuit arrangements than does the standard op amp; because as the curves indicate, the user may select the optimum circuit conditions for a speci?c application simply by varying the bias conditions of each ampli?er. if low power consumption, low bias, and low offset current, or high input impedance are primary design requirements, then low current operating conditions may be selected. on the other hand, if operation into a moderate load impedance is the primary consideration, then higher levels of bias may be used. bias consideration for op amp applications the operational transconductance ampli?ers allow the circuit designer to select and control the operating conditions of the circuit merely by the adjustment of the ampli?er bias current i abc . this enables the designer to have complete control over transconductance, peak output current and total power consumption independent of supply voltage. in addition, the high output impedance makes these ampli?- ers ideal for applications where current summing is involved. the design of a typical operational ampli?er circuit (figure 19) would proceed as follows: circuit requirements closed loop voltage gain = 10 (20db) offset voltage adjustable to zero current drain as low as possible supply voltage = 6v maximum input voltage = 50mv input resistance = 20k w load resistance = 20k w device: ca3060 calculation 1. required transconductance g 21 . assume that the open loop gain a ol must be at least ten times the closed loop gain. therefore, the forward transconductance required is given by: g 21 = a ol /r l = 100/18k w @ 5.5ms (r l = 20k w in parallel with 200k w@ 18k w ) 2. selection of suitable ampli?er bias current. the ampli- ?er bias current is selected from the minimum value curve of transconductance (figure 11) to assure that the ampli?- er will provide suf?cient gain. for the required g 21 of 5.5ms an ampli?er bias current i abc of 20 m a is suitable. 3. determination of output swing capability. for a closed loop gain of 10 the output swing is 0.5v and the peak load current is 25 m a. however, the amplifier must also supply the necessary current through the feedback resistor and if r s = 20k w, then r f = 200k w for a cl = 10. therefore, the feedback loading = 0.5v/200k w = 2.5 m a. the total ampli?er current output requirements are, there- fore, 27.5 m a. referring to the data given in figure 5, we see that for an ampli?er bias current of 20 m a the ampli?er output current is 40 m a. this is obviously adequate and it is not necessary to change the ampli?er bias current i abc . inverting input v+ q 15 q 14 d 7 d 8 d 6 d 5 q 10 q 11 q 7 q 9 q 13 output q 8 q 6 d 4 q 12 q 3 - q 5 q 4 d 2 d 3 q 2 non- inverting input + amplifier bias current (abc) v- d 1 q 1 v- complete ota circuit figure 18. complete schematic diagram showing bias regulator and one of the three operational transconductance amplifiers 8 15 amplifier 1 13 14 16 r abc 3 -6v r f r s - + 0.1 to +6v r l 20k w 200k w 0.1 20k w 560k w input r offset <4m w -6v +6v 2.2m w 18k w +6v figure 19. 20db amplifier using the ca3060 ca3060
3-8 4. calculation of bias resistance. for minimum supply current drain the amplifier bias current i abc should be fed directly from the supplies and not from the bias regulator. the value of the resistor r abc may be directly calculated using ohms law. 5. calculation of offset adjustment circuit. in order to reduce the loading effect of the offset adjustment circuit on the power supply, the offset control should be arranged to provide the necessary offset current. the source resistance of the non-inverting input is made equal to the source resistance of the inverting input, i.e., because the maximum offset voltage is 5mv plus an additional increment due to the offset current (figure 2) ?owing through the source resistance (i.e., 200 x 10 -9 x 18 x 10 3 v), the offset voltage range = 5mv + 3.6mv = 8.6mv. the current necessary to provide this offset is: with a supply voltage of 6v, this current can be provided by a 10m w resistor. however, the stability of such a resistor is often questionable and a more realistic value of 2.2m w was used in the ?nal circuit. capacitance effects the ca3060 is designed to operate at such low power levels that high impedance circuits must be employed. in designing such circuits, particularly feedback ampli?ers, stray circuit capacitance must always be considered because of its adverse effect on frequency response and stability. for example a 10k w load with a stray capacitance of 15pf has a time constant of 1mhz. figure 20 illustrates how a 10k w 15pf load modi?es the frequency characteristic. capacitive loading also has an effect on slew rate; because the peak output current is established by the ampli?er bias current, i abc (figure 5), the maximum slew rate is limited to the maximum rate at which the capacitance can be charged by the i om . therefore, sr = dv/dt = i om /c l , where c l is the total load capacitance including strays. this relationship is shown graphically in figure 21. when measuring slew rate for this data sheet, care was taken to keep the total capacitive loading to 13pf. phase compensation in many applications phase compensation will not be required for the ampli?ers of the ca3060. when needed, compensation may easily be accomplished by a simple rc network at the input of the ampli?er as shown in figure 17. the values given in figure 17 provide stable operation for the critical unity gain condition, assuming that capacitive loading on the output is 13pf or less. input phase compen- sation is recommended in order to maintain the highest possible slew rate. in applications such as integrators, two otas may be cascaded to improve current gain. compensation is best accomplished in this case with a shunt capacitor at the output of the ?rst ampli?er. the high gain following compen- sation assures a high slew rate. r abc v sup v abc C i abc ------------------------------------- = r abc 12 0.63 C 20 10 6 C ------------------------- = r abc 568.5k w or 560k w @ = 20k w 200k w 20k w 200k w + --------------------------------------- - 18k w @ 8.6mv 18k w ----------------- - 0.48 m a @ relative gain (db) frequency (mhz) 0 -20 -40 -60 -80 0.01 0.1 1.0 10 100 r l = 10k w c l = 15pf r l = 10k w c l = 0 figure 20. effect of capacitive loading on frequency response slew rate (v/ m s) 1000 100 10 1 0.01 0.1 1.0 10 100 abcd e f g h i j k l a. c l = 10,000pf b. c l = 3,000pf c. c l = 1000pf d. c l = 300pf e. c l = 100pf f. c l = 30pf g. c l = 10pf h. c l = 3pf i. c l = 1pf j. c l = 0.3pf k. c l = 0.1pf l. c l = 0.03pf peak output current (ma) figure 21. effect of load capacitance on slew rate ca3060
3-9 typical applications having determined the operating points of the ca3060 ampli?ers, they can now function in the same manner as conventional op amps, and thus, are well suited for most op amp applications, including inverting and non-inverting ampli?ers, integrators, differentiators, summing ampli?ers etc. tri-level comparator tri-level comparator circuits are an ideal application for the ca3060 since it contains the requisite three ampli?ers. a tri- level comparator has three adjustable limits. if either the upper lower limit is exceeded, the appropriate output is activated until the input signal returns to a selected intermediate limit. tri-level comparators are particularly suited to many industrial control applications. circuit description figure 23 shows the block diagram of a tri-level comparator using the ca3060. two of the three ampli?ers are used to compare the input signal with the upper limit and lower limit reference voltages. the third ampli?er is used to compare the input signal with a selected value of intermediate limit reference voltage. by appropriate selection of resistance ratios this intermediate limit may be set to any voltage between the upper limit and lower limit values. the output of the upper limit and lower limit comparator sets the corre- sponding upper or lower limit ?ip-?op. the activated ?ip-?op retains its state until the third comparator (intermediate limit) in the ca3060 initiates a reset function, thereby indicating that the signal voltage has returned to the intermediate limit selected. the ?ip-?ops employ two ca3086 transistor array ics, with circuitry to provide separate set and positive output terminals. v+ = 6v load 10k 4.7k 8 q 1 100 6 7 5.1k 5 1 3 2 4 150k 9 11 10 12 13 14 v+ = 6v load 4.7k 10k 8 q 2 100 6 7 150k 5 1 3 2 4 5.1k 9 11 10 14 12 13 saturates when lower limit is exceeded lower limit flip-flop upper limit flip-flop ca3086 ca3086 saturates when upper limit is exceeded 9 set when lower limit is exceeded 4 5 - + 1/3 ca3060 5.1k 5.1k - + 1/3 ca3060 reset 7 when intermediate reference limit is exceeded when upper limit is exceeded set lower limit reference e l r 3 10k 11 12 intermediate limit reference voltage 5.1k r 4 10k - + 1/3 ca3060 13 14 16 upper limit reference voltage e u 5.1k 5.1k 13k v+ = 6v input signal (e s ) r 2 1k 6 10 i abc i abc 15 i abc regulator in ca3060 2 8 25k 1 20k v- = -6v 3 v+ = 6v notes: 9. items in dashed boxes are external to the ca3086. all resistance values are in ohms. voltage r 1 1k e u - e l 2 10. e s e u e l C 2 ------------------- - < q 1 (off), q 2 (off) = e s e u q 1 (on), q 2 (off) = > e l e u q 2 (on), q 1 (off) = < figure 22. tri-level comparator circuit ca3060
3-10 the circuit diagram of a tri-level comparator appears in figure 22. power is provided for the ca3060 via terminal 3 and 8 by 6v supplies and the built-in regulator provides ampli?er bias current (i abc ) to the three ampli?ers via terminal 1. lower limit and upper limit reference voltages are selected by appro- priate adjustment of potentiometers r 1 and r 2 , respectively. when resistors r 3 and r 4 are equal in value (as shown), the intermediate limit reference voltage is automatically estab- lished at a value midway between the lower limit and upper limit values. appropriate variation of resistors r 3 and r 4 per- mits selection of other values of intermediate limit voltage. input signal (e s ) is applied to the three comparators via termi- nals 5, 12 and 14. the set output lines trigger the appropri- ate ?ip-?op whenever the input signal reaches a limit value. when the input signal returns to an intermediate value, the common ?ip-?op reset line is energized. the loads in the circuits, shown in figure 22 are 5v, 25ma lamps. active filters - using the ca3060 as a gyrator the high output impedance of the otas makes the ca3060 ideally suited for use as a gyrator in active ?lter applications. figure 24 shows two otas of the ca3060 connected as a gyrator in an active ?lter circuit. the otas in this circuit can make a 3 m f capacitor function as a ?oating 10kh inductor across terminals a and b. the measured q of 13 (at a frequency of 1hz) of this inductor compares favorably with a calculated q of 16. the 20k w to 2m w attenuators in this circuit extend the dynamic range of the ota by a factor of 100. the 100k w potentiometer, across v+ and v-, tunes the inductor by varying the g 21 of the otas, thereby changing the gyration resistance. three channel multiplexer figure 25 shows a schematic of a three channel multiplexer using a single ca3060 and a 3n153 mosfet as a buffer and power ampli?er. when the ca3060 is connected as a high input impedance voltage follower, and strobe on, each ampli?er is activated and the output swings to the level of the input of the ampli?er. the cascade arrangement of each ca3060 ampli?er with the mosfet provides an open loop voltage gain in excess of 100db, thus assuring excellent accuracy in the voltage follower mode with 100% feedback. operation at 6v is also possible with several minor changes. first, the resistance in series with the ampli?er bias current (i abc ) ter- minal of each ampli?er should be decreased to maintain 100 m a of strobe on current at this lower supply voltage. second, the drain resistance for the mosfet should be ca3060 tri-level detector ca3086 flip-flop ca3086 flip-flop set reset set v+ v+ positive output (when upper upper limit reference voltage intermediate limit refer- ence voltage input signal limit is reached) positive output (when lower limit is reached) lower limit reference voltage v+ v- - + - + - + figure 23. functional block diagram of a tri-level comparator amp 1 3 v+ = 6v amp 2 15 8 v- = -6v 10 100k w v+ v- 560k w 560k w 12 9 11 16 14 20 3 m f 2m w 13 20k w 20k w terminal a 2m w l = 10kh terminal b k w 20 k w figure 24. two operational transconductance amplifiers of the ca3060 connected as a gyrator in an active filter circuit - + 3 4 5 2k w 2k w v+ = 15v 0.01 m f 7 8 6 300k w strobe v- = -15v - + 2k w 2k w 9 300k w strobe 12 11 10 - + 2k w 2k w 300k w strobe 13 14 15 16 3 390 w 0.001 m f 4 2 v+ = 15v 0.02 m f output 3n153 v- = -15v +15v -15v strobe on strobe off 3k w figure 25. three channel multiplexer ca3060
3-11 decreased to maintain the same value of source current. the low cost dual gate protected mosfet, 40841 type, may be used when operating at the low supply voltage. the phase compensation network consists of a single 390 w resistor and a 1000pf capacitor, located at the interface of the ca3060 output and the mosfet gate. the bandwidth of the system is 1.5mhz and the slew rate is 0.3v/ m s. the system slew rate is directly proportional to the value of the phase compensation capacitor. thus, with higher gain settings where lower values of phase compensation capacitors are possible, the slew rate is proportionally increased. non-linear applications am modulator (two quadrant multiplier) figure 26 shows ampli?er 3 of the ca3060 used in an am modulator or two quadrant multiplier circuit. when modula- tion is applied to the ampli?er bias input, terminal b, and the carrier frequency to the differential input, terminal a, the waveform, shown in figure 26 is obtained. figure 26 is a result of adjusting the input offset control to balance the circuit so that no modulation can occur at the output without a carrier input. the linearity of the modulator is indicated by the solid trace of the superimposed modulating frequency. the maximum depth of modulation is determined by the ratio of the peak input modulating voltage to v-. the two quadrant multiplier characteristic of this modulator is easily seen if modulation and carrier are reversed as shown in figure 26. the polarity of the output must follow that of the dif- ferential input; therefore, the output is positive only during, the positive half cycle of the modulation and negative only in the second half cycle. note, that both the input and output signals are referenced to ground. the output signal is zero when either the differential input or i abc are zero. four quadrant multiplier the ca3060 is also useful as a four quadrant multiplier. a block diagram of such a multiplier, utilizing ampli?ers 1, 2 and 3 is shown in figure 27 and a typical circuit is shown in figure 28. the multiplier consists of a single ca3060 and, as in the two quadrant multiplier, exhibits no level shift between input and output. in figure 27, ampli?er 1 is connected as an inverting ampli?er for the x-input signal. the output current of ampli?er 1 is calculated as follows: ampli?er 2 is a non-inverting ampli?er so that because the ampli?er output impedances are high, the load current is the sum of the two output currents, for an output voltage the transconductance is approximately proportional to the ampli?er bias current; therefore, by varying the bias current the g 21 is also controlled. ampli?er 2 bias current is propor- tional to the y-input signal and is expressed as hence, bias for ampli?er 1 is derived from the output of ampli?er 3 which is connected as a unity gain inverting ampli?er. i abc(1) , therefore, varies inversely with v y . and by the same reasoning as above combining equations 3, 5 and 6 yields: v o ? v x x k x r l {[(v-) + v y ] - [(v-) - v y ]} or v o ? 2kr l v x v y i o (1) = [-v x ] [g 21 (1)] eq. 1 io(2) = [+vx] [g 21 (2)] eq. 2 v o = v x r l [g 21 (2) - g 21 (1)] eq. 3 g 21 (2) ? k [(v-) + v y ] eq. 5 g 21 (1) ? k [(v-) - v y ] eq. 6 i abc(2) v- () v y + r 1 ------------------------ ? eq. 4 6 8 amp 3 3 -6v +6v - + 100k w modulated output 4 5 1m w 1m w 1k w 10k w carrier v+ v- 10k w modulation term. a term. b 100k w 1k w figure 26. two quadrant multiplier circuit using the ca3060 with associated waveforms 7 ca3060
3-12 figure 28 shows the actual circuit including all the adjust- ments associated with differential input and an adjustment for equalizing the gains of ampli?ers 1 and 2. adjustment of the circuit is quite simple. with both the x and y voltages at zero, connect terminal 10 to terminal 8. this procedure disables ampli?er 2 and permits adjusting the offset voltage of ampli?er 1 to zero by means of the 100k w potentiometer. next, remove the short between terminal 10 and 8 and connect terminal 15 to terminal 8. this step disables ampli?er 1 and permits ampli?er 2 to be zeroed with the other potentiometer. with ac signals on both the x and y inputs, r 3 and r 11 are adjusted for symmetrical output signals. figure 29 shows the output waveform with the multiplier adjusted. the voltage waveform in figure 29a shows suppressed carrier modulation of 1khz carrier with a triangular wave. figures 29b and 29c, respectively, show the squaring of a triangular wave and a sine wave. notice that in both cases the output is always positive and returns to zero after each cycle. amp - + 1 amp 2 amp 3 y input + - i abc (1) r 1 r 2 i abc (2) + - r f r in i o(2) r l i o(1) x input v o figure 27. four quadrant multiplier amp 1 4 13 ca3060 15 14 output x input 1m w 270 w 270 w 100 w 270 w 1m w 1m w 1m w 16 amp 3 4 7 200k w 51 k w 5 y input 24k w 100 w 0.02 m f 1.1m w 6 100k w 100k w v+ v- 3 560k w 560k w 240k w amp 2 10 11 12 9 8 51k w 270 w figure 28. typical four quadrant multiplier circuit figure 29a. figure 29b. figure 29c. figure 29. voltage waveforms of four quadrant multiplier circuit ca3060

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